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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a precision rail-to-rail input & output operational amplifiers op184/op284/op484 ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features single-supply operation wide bandwidth: 4 mhz low offset voltage: 65 m v unity-gain stable high slew rate: 4.0 v/ m s low noise: 3.9 nv/ ? hz applications battery powered instrumentation power supply control and protection telecom dac output amplifier adc input buffer general description the op184/op184/op284/op484 are single, dual and quad single-supply, 4 mhz bandwidth amplifiers featuring rail-to-rail inputs and outputs. they are guaranteed to operate from +3 to +36 (or 1.5 to 18) volts and will function with a single supply as low as +1.5 volts. these amplifiers are superb for single supply applications re- quiring both ac and precision dc performance. the combination of bandwidth, low noise and precision makes the op1 84/op284/ op484 useful in a wide variety of applications, including filters and instrumentation. other applications for these amplifiers include portable telecom equipment, power supply control and protection, and as amplifi- ers or buffers for transducers with wide output ranges. sensors requiring a rail-to-rail input amplifier include hall effect, piezo electric, and resistive transducers. the ability to swing rail-to-rail at both the input and output en- ables designers to build multistage filters in single-supply sys- tems and maintain high signal-to-noise ratios. the op184/op284/op484 are specified over the hot extended industrial (C40 c to +125 c) temperature range. the single and dual are available in 8-pin plastic dip plus so surface mount packages. the quad op484 is available in 14-pin plastic dips and 14-lead narrow-body so packages. pin configurations 8-lead epoxy dip (p suffix) 8-lead so (s suffix) 1 2 3 4 8 7 6 5 op184 + nc = no connect null ?n a +in a v nc v+ out a null 8-lead epoxy dip (p suffix) 8-lead so (s suffix) 1 2 3 45 6 7 8 out a ?n a +in a v op-482 v+ out b ?n b +in b op284 14-lead epoxy dip (p suffix) 14-lead narrow-body so (s suffix) 1 2 3 4 8 7 6 5 ? op484 out a ?n a +in a v+ out d ?n d +in d v 14 13 12 11 9 10 +in b ?n b out b +in c ?n c out c + ? ?
op184/op284/op484Cspecifications electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage op184/284e grade v os (note 1) 65 m v C40 c t a +125 c 165 m v offset voltage op184/284f grade v os 125 m v C40 c t a +125 c 350 m v offset voltage op184 484e grade v os 75 m v C40 c t a +125 c 175 m v offset voltage op184 484f grade v os 150 m v C40 c t a +125 c 450 m v input bias current i b 60 300 na C40 c t a +125 c 500 na input offset current i os 250na C40 c t a +125 c50na input voltage range 0+5v common-mode rejection ratio cmrr v cm = 0 v to 5 v 60 db common-mode rejection ratio cmrr v cm = 1.0 v to 4.0 v, C40 c t a +125 c86 db large signal voltage gain a vo r l = 2 k w , 1 v v o 4 v 50 240 v/mv r l = 2 k w , C40 c t a +125 c 25 v/mv bias current drift d i b / d t 150 pa/ c output characteristics output voltage high v oh i l = 1.0 ma +4.85 v output voltage low v ol i l = 1.0 ma 125 mv output currrent i out 6.5 ma power supply power supply rejection ratio psrr v s = +2.0 v to +10 v, C40 c t a +125 c76 db supply current/amplifier i sy v o = 2.5 v, C40 c t a +125 c 1.25 ma supply voltage range v s +3 +36 v dynamic performance slew rate sr r l = 2 k w 1.65 2.4 v/ m s settling time t s to 0.01%, 1.0 v step 2.5 m s gain bandwidth product gbp 3.25 mhz phase margin ?o 45 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 0.3 m v p-p voltage noise density e n f = 1 khz 3.9 nv/ ? hz current noise density i n 0.4 pa/ ? h z notes 1 input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. specifications subject to change without notice. rev. 0 C2C (@ v s = +5.0 v, v cm = 2.5 v, t a = +25 8 c unless otherwise noted)
rev. 0 C3C op184/op284/op484 electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage op184/284e grade v os (note 1) 65 m v C40 c t a +125 c 165 m v offset voltage op184/284f grade v os 125 m v C40 c t a +125 c 350 m v offset voltage op184 484e grade v os 100 m v C40 c t a +125 c 200 m v offset voltage op184 484f grade v os 150 m v C40 c t a +125 c 450 m v input bias current i b 60 300 na C40 c t a +125 c 500 na input offset current i os C40 c t a +125 c50na input voltage range 0+3v common-mode rejection ratio cmrr v cm = 0 v to 3 v 60 db common-mode rejection ratio cmrr v cm = 0 v to 3 v, C40 c t a +125 c56 db output characteristics output voltage high v oh i l = 1.0 ma +2.85 v output voltage low v ol i l = 1.0 ma 125 mv power supply power supply rejection ratio psrr v s = 1.25 v to 1.75 v 76 db supply current/amplifier i sy v o = 1.5 v, C40 c t a +125 c 1.15 ma dynamic performance gain bandwidth product gbp 3 mhz noise performance voltage noise density e n f = 1 khz 3.9 nv/ ? hz notes 1 input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. specifications subject to change without notice. (@ v s = +3.0 v, v cm = 1.5 v, t a = +25 8 c unless otherwise noted)
rev. 0 C4C op184/op284/op484 electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage op184/284e grade v os (note 1) 100 m v C40 c t a +125 c 200 m v offset voltage 284f grade v os 175 m v C40 c t a +125 c 375 m v offset voltage 484e grade v os 150 m v C40 c t a +125 c 300 m v offset voltage 484f grade v os 250 m v C40 c t a +125 c 500 m v input bias current i b 80 300 na C40 c t a +125 c 500 na input offset current i os C40 c t a +125 c50na input voltage range C15 +15 v common-mode rejection ratio cmrr v cm = C14.0 v to +14.0 v, C40 c t a +125 c86 90 db common-mode rejection ratio cmrr v cm = C15.0 v to +15.0 v 80 db large signal voltage gain a vo r l = 2 k w , C10 v v o 10 v 150 1000 v/mv r l = 2 k w , C40 c t a +125 c 75 v/mv offset voltage drift e grade d v os / d t 0.2 2.00 m v/ c bias current drift d i b / d t 150 pa/ c output characteristics output voltage high v oh i l = 1.0 ma +14.8 v output voltage low v ol i l = 1.0 ma C14.875 v output current i out 10 ma power supply power supply rejection ratio psrr v s = 2.0 v to 18 v, C40 c t a +125 c90 db supply current/amplifier i sy v o = 0 v, C40 c t a +125 c 1.75 ma supply current/amplifier i sy v s = 18 v, C40 c t a +125 c 2.0 ma dynamic performance slew rate sr r l = 2 k w 2.4 4.0 v/ m s full-power bandwidth bw p 1% distortion, r l = 2 k w , v o = 29 v p-p 35 khz settling time t s to 0.01%, 10 v step 4 m s gain bandwidth product gbp 4.25 mhz phase margin ?o 50 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 0.3 m v p-p voltage noise density e n f = 1 khz 3.9 nv/ ? hz current noise density i n 0.4 pa/ ? hz notes 1 input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. specifications subject to change without notice. (@ v s = 6 15.0 v, v cm = 0 v, t a = +25 8 c unless otherwise noted) wafer test limits parameter symbol conditions limit units offset voltage op284 v os 65 m v max offset voltage op484 v os 75 m v max input bias current i b 300 na max input offset current i os 50 na max input voltage range v cm vC to v+ v min common-mode rejection ratio cmrr v cm = +1 v to +4 v 86 db min power supply rejection ratio psrr v s = 2 v to 18 v 90 db min large signal voltage gain a vo r l = 2 k w 50 v/mv min output voltage high v oh i l = 1.0 ma 4.85 v min output voltage low v ol i l = 1.0 ma 125 mv max supply current/amplifier i sy v o = 0 v, r l = 1.25 ma max note electrical tests and wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. (@ v s = +5.0 v, v cm = 2.5 v, t a = +25 8 c unless otherwise noted)
rev. 0 C5C op184/op284/op484 absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v differential input voltage 2 . . . . . . . . . . . . . . . . . . . . . . 0.6 v output short-circuit duration to gnd 3 . . . . . . . . . indefinite storage temperature range p, s packages . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range op184/op284/op484e, f . . . . . . . . . . . . . C40 c to +125 c junction temperature range p, s packages . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c package type q ja 3 q jc units 8-pin plastic dip (p) 103 43 c/w 8-pin soic (s) 158 43 c/w 14-pin plastic dip (p) 83 39 c/w 14-pin soic (s) 92 27 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 for input voltages greater than 0.6 volts the input current should be limited to less than 5 ma to prevent degradation or destruction of the input devices. 3 q ja is specified for the worst case conditions; i.e., q ja is specified for device in socket for cerdip, and p-dip packages, q ja is specified for device soldered in circuit board for soic package. ordering guide temperature package package model range description option op184ep C40 c to +125 c 8-pin plastic dip n-8 op184es C40 c to +125 c 8-pin soic so-8 op184fp C40 c to +125 c 8-pin plastic dip n-8 op184fs C40 c to +125 c 8-pin soic so-8 op284ep C40 c to +125 c 8-pin plastic dip n-8 OP284ES C40 c to +125 c 8-pin soic so-8 op284fp C40 c to +125 c 8-pin plastic dip n-8 op284fs C40 c to +125 c 8-pin soic so-8 op484ep C40 c to +125 c 14-pin plastic dip n-14 op484es C40 c to +125 c 14-pin soic so-14 op484fp C40 c to +125 c 14-pin plastic dip n-14 op484fs C40 c to +125 c 14-pin soic so-14 op284 die size 0.065 0.092 inch, 5,980 sq. mils substrate (die backside) is connected to vC. transistor count, 62. op484 die size 0.080 0.110 inch, 8,800 sq. mils substrate (die backside) is connected to vC. transistor count, 120. r3 q1 ?n +in ql1 ql2 q4 q3 q2 qb5 qb6 rb2 qb3 r1 q5 r2 qb4 jb2 qb1 cb1 n+ p+ m qb2 cc1 q9 q7 q11 q8 q6 q10 q12 qb7 qb8 qb9 rb1 jb1 tp r4 r5 r6 rb3 cff r7 r8 q13 q14 r10 q15 rb4 qb10 cc2 c o q17 q16 r11 q18 v cc out v ee r9 figure 1. simplified schematic
input offset voltage ?? quantity 300 0 ?00 ?5 100 ?0 ?5 0 25 50 75 270 180 90 60 30 240 210 120 150 v s = +3v t a = +25 c v cm = 1.5v figure 2. input offset voltage distribution input offset voltage ?? quantity 300 0 ?00 ?5 100 ?0 ?5 0 25 50 75 270 180 90 60 30 240 210 120 150 v s = +5v t a = +25 c v cm = 2.5v figure 3. input offset voltage distribution input offset voltage ?? quantity 200 0 ?25 ?00 125 ?5 ?0 0 50 75 100 175 100 75 50 25 150 125 v s = 15v t a = +25 c ?5 25 figure 4. input offset voltage distribution C6C offset voltage drift, tcv os ??/ c quantity 300 0 0 0.25 1.5 0.50 0.75 1.0 1.25 250 200 150 100 50 v s = +5v ?0 c t a +125 c figure 5. input offset voltage drift distribution offset voltage drift, tcv os ??/ c quantity 300 0 0 0.25 1.5 0.50 0.75 1.0 1.25 250 200 150 100 50 v s = 15v ?0 c t a +125 c figure 6. input offset voltage drift distribution temperature ? c input bias current ?na ?0 ?0 ?0 125 25 85 ?5 ?0 ?5 ?0 ?5 ?0 ?5 v s = +5v v s = 15v v cm = v s /2 figure 7. bias current vs. temperature common mode voltage ?volts input bias current ?na 500 ?00 ?5 ?0 15 ? 5 10 0 400 300 200 100 0 ?00 ?00 ?00 ?00 v s = 15v figure 8. input bias current vs. common-mode voltage load current ?ma output voltage ?mv 1,000 100 10 0.01 0.1 10 1 source sink v s = 15v figure 9. output voltage to supply rail vs. load current temperature ? c supply current/amplifier ?ma 1.2 0.5 1.1 0.8 0.7 0.6 1.0 0.9 ?0 125 25 85 v s = 15v v s = +5v v s = +3v figure 10. supply current vs. temperature op184/op284/op484Ctypical performance characteristics rev. 0
rev. 0 C7C op184/op284/op484 supply voltage ?volts supply current (per amplifier) ?ma 1.50 0 0 2.5 20 5.0 10 12.5 15 1.25 1.0 0.75 0.5 0.25 17.5 7.5 t a = +25 c figure 11. supply current vs. supply voltage temperature ? c short circuit current ?ma 50 0 ?0 125 40 30 20 10 v s = 15v ?5 0 25 75 50 100 v s = +5v, v cm = +2.5v +i sc ? sc ? sc +i sc figure 12. short circuit current vs. temperature 0 45 90 135 180 225 270 phase shift ?degrees frequency ?hz open-loop gain ?db 60 10k 100k 10m 1m 40 20 0 ?0 80 50 10 30 ?0 ?0 v s = +5v t a = +25 c no load figure 13. open-loop gain and phase vs. frequency (no load) 0 45 90 135 180 225 270 phase shift ?degrees frequency ?hz open-loop gain ?db 60 10k 100k 10m 1m 40 20 0 ?0 80 50 10 30 ?0 ?0 v s = +3v t a = +25 c no load figure 14. open-loop gain and phase vs. frequency (no load) 0 45 90 135 180 225 270 phase shift ?degrees frequency ?hz open-loop gain ?db 60 10k 100k 10m 1m 40 20 0 ?0 80 50 10 30 ?0 ?0 v s = 15v t a = +25 c no load figure 15. open-loop gain and phase vs. frequency (no load) temperature ? c open-loop gain ?v/mv 2.5k 0 ?0 125 2k 1.5k 1k 500 v s = 15v ?0v < v o < 10v r l = 2k w ?5 0 25 75 50 100 v s = +5v 1v < v o < 4v r l = 2k w figure 16. open-loop gain vs. temperature frequency ?hz 30 10 closed-loop gain ?db 40 60 10 ?0 100 10k 1m 10m ?0 v s = +5v r l = 2k w t a = +25 c ?0 ?0 0 20 50 1k 100k figure 17. closed-loop gain vs. frequency (2 k w load) frequency ?hz 30 10 closed-loop gain ?db 40 60 10 ?0 100 10k 1m 10m ?0 v s = 15v r l = 2k w t a = +25 c ?0 ?0 0 20 50 1k 100k figure 18. closed-loop gain vs. frequency (2 k w load) frequency ?hz 30 10 closed-loop gain ?db 40 60 10 ?0 100 10k 1m 10m ?0 v s = +3v r l = 2k w t a = +25 c ?0 ?0 0 20 50 1k 100k figure 19. closed-loop gain vs. frequency (2 k w load)
frequency ?hz 210 100 output impedance ? w 240 300 150 0 1k 100k 10m 90 v s = +5v t a = +25 c 60 30 120 180 270 10k 1m a v = 100 a v = 1 a v = 10 figure 20. output impedance vs. frequency frequency ?hz 210 100 output impedance ? w 240 300 150 0 1k 100k 10m 90 v s = 15v t a = +25 c 60 30 120 180 270 10k 1m a v = 100 a v = 1 a v = 10 figure 21. output impedance vs. frequency frequency ?hz 210 100 output impedance ? w 240 300 150 0 1k 100k 10m 90 v s = +3v t a = +25 c 60 30 120 180 270 10k 1m a v = 100 a v = 1 a v = 10 figure 22. output impedance vs. frequency frequency ?hz 3 1k maximum output swing ?vp-p 4 5 2 0 10k 100k 1m 10m 1 v s = +5v v in = 0.5?.5v r l = 2k w t a = +25 c figure 23. maximum output swing vs. frequency frequency ?hz 20 1k maximum output swing ?vp-p 25 30 15 5 0 10k 100k 1m 10m 10 v s = 15v v in = 14v r l = 2k w t a = +25 c figure 24. maximum output swing vs. frequency frequency ?hz 120 100 cmrr ?db 140 180 80 ?0 1k 100k 10m 40 20 0 60 100 160 10k 1m v s = 15v v s = +5v t a = +25 c v s = +3v figure 25. cmrr vs. frequency frequency ?hz 100 100 psrr ?db 120 160 60 ?0 1k 100k 10m 20 t a = +25 c 0 ?0 40 80 140 10k 1m v s = 15v v s = +5v v s = +3v figure 26. psrr vs. frequency capacitive load ?pf overshoot ?% 80 70 0 10 100 1000 60 50 40 30 20 10 ?s +os v s = 2.5v t a = +25 c, a vcl = 1 v in = 50mv figure 27. small signal overshoot vs. capacitive load temperature ? c slew rate ?v/? 7 0 ?0 125 ?5 0 75 100 6 3 2 1 5 4 25 50 +slew rate ?lew rate v s = 15v r l = 2k w v s = +5v r l = 2k w +slew rate ?lew rate figure 28. slew rate vs.temperature rev. 0 C8C op184/op284/op484Ctypical performance characteristics
rev. 0 C9C op184/op284/op484 30 0 1000 15 5 10 25 20 100 10 frequency C hz 1 2.5v v s 15v t a = +25 c noise density e nv/ ? hz figure 29. voltage noise density vs. frequency 10 0 1000 6 2 4 8 100 10 frequency C hz 1 current noise density C pa/ ? hz 2.5v v s 15v t a = +25 c figure 30. current noise density vs. frequency settling time C s step size C volts 5 C5 01 6 24 4 3 2 1 0 5 3 C1 C2 C3 C4 v s = +5v t a = +25 c 0.1% 0.01% figure 31. se ttling time vs. step size settling time C s step size C volts 10 C10 01 6 24 8 6 4 2 0 5 3 C2 C4 C6 C8 v s = 15v t a = +25 c 0.1% 0.01% figure 32. settling time vs. step size 10 0% 100 90 1s 10mv v s = 15v a v = 100k e n = 0.3vp-p figure 33. 0.1 hz to 10 hz noise 10 0% 100 90 1s v s = +5v, 0v a v = 100k e n = 0.3vp-p 10mv figure 34. 0.1 hz to 10 hz noise frequency C hz 100 100 120 160 60 C40 1k 100k 10m 20 0 C20 40 80 140 10k 1m v s = 15v v s = +3v t a = +25 c channel separation e db figure 35. channel separation vs. frequency 10 0% 100 90 1s 100mv v s = +5v a v = 1 r l = open c l = 300pf t a = +25 c +400mv 0v figure 36. small signal transient response 10 0% 100 90 1s 100mv v s = +5v a v = 1 r l = 2k w c l = 300pf t a - +25 c 400mv 0v figure 37. small signal transient response
rev. 0 C10C op184/op284/op484 frequency C hz thd+n C % 0.1 0.010 0.0005 20 100 10k 1k 0.001 20k v o = 0.75v v o = 2.5v v o = 1.5v a v = 1000 v s = 2.5v r l = 2k w figure 40. total harmonic distortion vs. frequency 10 0% 100 90 500ns 100mv v s = 1.5v a v = 1 no load t a = +25 c 200mv 0v e200mv figure 38. small signal transient response 200mv 0v C200mv 10 0% 100 90 1s 100mv v s = 0.75v a v = 1 no load t a = +25 c figure 39. small signal transient response applications functional description the op284 and op484 are precision single-supply, rail-to-rail operational amplifiers. intended for the portable instrumenta- tion marketplace, the op184/op284/op484 combines the at- tributes of precision, wide bandwidth, and low noise to make it a superb choice in those single supply applications that require both ac and precision dc performance. other low supply voltage applications for which the op284 is well suited are active filters, audio microphone preamplifiers, power supply control, and tele- com. to combine all of these attributes with rail-to-rail input/ output operation, novel circuit design techniques are used. d1 d2 q4 r2 4k v pos i1 r1 4k q3 q1 q2 r4 3k i2 r3 3k v 01 Cin v 02 v neg +in figure 41. op284 equivalent input circuit for example, figure 41 illustrates a simplified equivalent circuit for the op184/op284/op484s input stage. it is comprised of an npn differential pair, q1-q2, and a pnp differential pair, q3-q4, operating concurrently. diode network d1-d2 serves to clamp the applied differential input voltage to the op284, thereby protecting the input transistors against avalanche dam- age. input stage voltage gains are kept low for input rail-to-rail operation. the two pairs of differential output voltages are con- nected to the op284s second stage which is a compound folded cascode gain stage. it is also in the second gain stage where the two pairs of differential output voltages are combined into a single-ended output signal voltage used to drive the output stage. a key issue in the input stage is the behavior of the input bias currents over the input common-mode voltage range. input bias currents in the op284 are the arithmetic sum of the base currents in q1-q3 and in q2-q4. as a result of this design approach, the input bias currents in the op284 not only exhibit different amplitudes, but also exhibit different polarities. this effect is best illustrated in figure 8. it is, therefore, of para- mount importance that the effective source impedances con- nected to the op284s inputs be balanced for optimum dc and ac performance. in order to achieve rail-to-rail output, the op284 output stage design employs a unique topology for both sourcing and sinking current. this circuit topology is illustrated in figure 42. as previously mentioned, the output stage is voltage-driven from the second gain stage. the signal path through the output stage is inverting; that is, for positive input signals, q1 provides the base current drive to q6 so that it conducts (sinks) current. for negative input signals, the signal path via q1-q2-d1-q4-q3 provides the base current drive for q5 to conduct (source) cur- rent. both amplifiers provide output current until they are forced into saturation which occurs at approximately 20 mv from negative rail and 100 mv from the positive supply rail. v pos i2 i1 q1 q3 q4 q2 v neg q5 v out q6 r6 r3 r2 r1 r4 input from second gain stage r5 d1 figure 42. op284 equivalent output circuit
rev. 0 C11C op184/op284/op484 thus, the saturation voltage of the output transistors sets the limit on the op284s maximum output voltage swing. output short circuit current limiting is determined by the maximum signal current into the base of q1 from the second gain stage. under output short circuit conditions, this input current level is approximately 100 m a. with transistor current gains around 200, the short circuit current limits are typically 20 ma. the output stage also exhibits voltage gain. this is accomplished by use of common-emitter amplifiers, and as a result the voltage gain of the output stage (thus, the open-loop gain of the device) exhibits a dependence to the total load resistance at the output of the op284. input overvoltage protection as with any semiconductor device, if conditions exist where the applied input voltages to the device exceed either supply voltage, then the devices input overvoltage i-v characteristic must be considered. when an overvoltage occurs, the amplifier could be damaged depending on the magnitude of the applied voltage and the magnitude of the fault current. figure 43 illustrates the over voltage i-v characteristic of the op284. this graph was generated with the supply pins connected to gnd and a curve tracers collector output drive connected to the input. 5 4 3 2 1 0 C1 C2 C3 C4 C5 C5C4C3C2C1012345 input current C ma input voltage C volts figure 43. input overvoltage i-v characteristics of the op284 as shown in the figure, internal p-n junctions to the op284 en- ergize and permit current flow from the inputs to the supplies when the input is 1.8 v more positive and 0.6 v more negative than the respective supply rails. as illustrated in the simplified equivalent circuit shown in figure 41, the op284 does not have any internal current limiting resistors; thus, fault currents can quickly rise to damaging levels. this input current is not inherently damaging to the device, provided that it is limited to 5 ma or less. for the op284, once the input exceeds the negative supply by 0.6 v, the input cur- rent quickly exceeds 5 ma. if this condition continues to exist, an external series resistor should be added at the expense of ad- ditional thermal noise. figure 44 illustrates a typical noninvert- ing configuration for an overvoltage protected amplifier where the series resistance, r s , is chosen such that: r s = v in ( max ) v supply 5 ma r1 r2 v in v out 1/2 op284 figure 44. a resistance in series with an input limits overvoltage currents to safe values for example, a 1 k w resistor will protect the op284 against input signals up to 5 v above and below the supplies. for other configurations where both inputs are used, then each input should be protected against abuse with a series resistor. again, in order to ensure optimum dc and ac performance, it is recom- mended to balance source impedance levels. for more informa- tion on the general overvoltage characteristics of amplifiers, please refer to the 1993 system applications guide , section 1, pages 56-69. this reference textbook is available from the ana- log devices literature center. output phase reversal some operational amplifiers designed for single-supply opera- tion exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. typically for single-supply bipolar op amps, the negative supply deter- mines the lower limit of their common-mode range. with these devices, external clamping diodes, with the anode connected to ground and the cathode to the inputs, prevent input signal ex- cursions from exceeding the devices negative supply (i.e., gnd), preventing a condition that could cause the output volt- age to change phase. jfet-input amplifiers may also exhibit phase reversal, and, if so, a series input resistor is usually re- quired to prevent it. the op284 is free from reasonable input voltage range restric- tions provided that the input voltages no greater than the supply voltages are applied. although the devices output will not change phase, large currents can flow through the input protec- tion diodes, as was shown in figure 43. therefore, the technique recommended in the input overvoltage protection section should be applied in those applications where the likelihood of input voltages exceeding the supply voltages is high. designing low noise circuits in single supply applications in single supply applications, devices like the op284 extend the dynamic range of the application through the use of rail-to-rail operation. in fact, the op284 family is the first of its kind to combine single supply, rail-to-rail operation and low noise in one device. it is the first device in the industry to exhibit an input noise voltage spectral density of less than 4 nv/ ? hz at 1 khz. it was also designed specifically for low-noise, single- supply applications, and as such some discussion on circuit noise concepts in single supply applications is appropriate.
rev. 0 C12C op184/op284/op484 referring to the op amp noise model circuit configuration illus- trated in figure 45, the expression for an amplifiers total equivalent input noise voltage for a source resistance level r s is given by: e nt = 2 e nr () 2 + i noa r () 2 [] + e noa () 2 , units in v hz where r s = 2r = effective, or equivalent, circuit source resistance, ( e noa ) 2 = op amp equivalent input noise voltage spectral power (1 hz bw), ( i noa ) 2 = op amp equivalent input noise current spectral power (1 hz bw), ( e nr ) 2 = source resistance thermal noise voltage power = (4ktr), k = boltzmanns constant = 1.38 10 C23 j/k, and t = ambient temperature of the circuit, in kelvin, = 273.15 + t a ( c) i noa e nr e noa r "noiseless" i noa e nr r "noiseless" ideal noiseless op amp r s = 2r figure 45. op amp noise circuit model used to determine total circuit equivalent input noise voltage and noise figure as a design aid, figure 46 illustrates the total equivalent input noise of the op284 and the total thermal noise of a resistor for comparison. note that for source resistance less than 1 k w , the equivalent input noise voltage of the op284 is dominant. total source resistance, r s ? w 100 100 equivalent thermal noise ?nv/ ? hz 1k 10k 100k 10 1 op284 total equivalent noise resistor thermal noise only frequency = 1khz t a = +25 c figure 46. op284 total noise vs. source resistance since circuit snr is the critical parameter in the final analysis, many times the noise behavior of a circuit is expressed in terms of its noise figure, nf. noise figure is defined to be the ratio of a circuits output signal-to-noise to its input signal-to-noise. an expression for a circuits nf in db and in terms of the opera- tional amplifier's voltage and current noise parameters defined previously is given by: nf ( db ) = 10 log 1 + e noa () 2 + i noa r s () 2 e nrs () 2 ? ? ? ? ? ? where nf ( db ) = noise figure of the circuit, expressed in db, r s = effective, or equivalent, source resistance presented to amplifier, ( e noa ) 2 = op284 noise voltage spectral power (1 hz bw), ( i noa ) 2 = op284 noise current spectral power (1 hz bw), ( e nrs ) 2 = source resistance thermal noise voltage power = (4ktr s ), circuit noise figure is straightforward to calculate because the signal level in the application is not required to determine it. however, many designers using nf calculations as the basis for achieving optimum snr believe that low noise figure is equal to low total noise. in fact, the opposite is true, as illustrated in figure 47. here, the noise figure of the op284 is expressed as a function of the source resistance level. note that the lowest noise figure for the op284 occurs at a source resistance level of 10 k w . however, figure 46 shows that this source resistance level and the op284 generate approximately 14 nv/ ? hz of total equivalent circuit noise. signal levels in the application would invariably be increased to maximize circuit snrnot an option in low voltage, single supply applications. total source resistance, r s ? w 6 100 noise figure ?db 1k 10k 100k 4 2 0 9 10 8 7 5 3 1 frequency = 1khz t a = +25 c figure 47. op284 noise figure vs. source resistance in single supply applications, it is, therefore, recommended for optimum circuit snr to choose an operational amplifier with the lowest equivalent input noise voltage and to choose source resistance levels consistent in maintaining low total circuit noise.
rev. 0 C13C op184/op284/op484 overdrive recovery the overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to its linear re- gion from a saturated condition. the recovery time is important in applications where the amplifier must recover quickly after a large transient event. the circuit shown in figure 48 was used to evaluate the op284s overload recovery time. the op284 takes approximately 2 m s to recover from positive saturation and approximately 1 m s to recover from negative saturation. v out 2 3 1 +5v 1/2 op284 8 4 r3 9k w r1 10k w r2 10k w v in 10v step ?v figure 48. output overload recovery test circuit a single-supply, +3 v instrumentation amplifier the op284s low noise, wide bandwidth, and rail-to-rail input/ output operation makes it ideal for low supply voltage applica- tions, such as in an two op amp instrumentation amplifier as shown in figure 49. the circuit utilizes the classic two op amp instrumentation amplifier topology, with four resistors to set the gain. the transfer equation of the circuit is identical to that of a noninverting amplifier. resistors r2 and r3 should be closely matched to each other as well as resistors (r1 + p1) and r4 to ensure good common-mode rejection performance. resistor networks should be used in this circuit for r2 and r3 because they exhibit the necessary relative tolerance matching for good performance. matched networks also exhibit tight relative resis- tor temperature coefficients for good circuit temperature stabil- ity. trimming potentiometer p1 is used for optimum dc cmr adjustment, and c1 is used to optimize ac cmr. with the cir- cuit values as shown, circuit cmr is better than 80 db over the frequency range of 20 hz to 20 khz. circuit rti (referred-to- input) noise in the 0.1 hz to 10 hz band is an impressively low 0.45 m v p-p. resistors rp1 and rp2 serve to protect the op284s inputs against input overvoltage abuse. capacitor c2 can be included to the limit circuit bandwidth and, therefore, wide bandwidth noise in sensitive applications. the value of this capacitor should be adjusted depending on the required closed-loop bandwidth of the circuit. the r4-c2 time constant creates a pole at a frequency equal to: f (3 db ) = 1 2 p r 4 c 2 v out r3 1.1k w 5 6 7 +3v a2 a1, a2 = 1/2 op284 gain = 1 + r4 r3 set r2 = r3 r1 + p1 = r4 8 4 r4 10k w c2 rp1 1k w rp2 1k w r2 1.1k w r1 9.53k w p1 500 w 3 2 1 c1 ac cmrr trim 5pf?0pf a1 v in figure 49. a single supply, +3 v low noise instrumenta- tion amplifier a +2.5 v reference from a +3 v supply in many single-supply applications, the need for a 2.5 v refer- ence often arises. many commercially available monolithic 2.5 v references require at least a minimum operating supply of 4 v. the problem is exacerbated when the minimum operating supply voltage is +3 v. the circuit illustrated in figure 50 is an example of a +2.5 v reference that operates from a single +3 v supply. the circuit takes advantage of the op284s rail-to-rail input/output voltage ranges to amplify an ad589s 1.235 v output to +2.5 v. the op284s low tcv os of 1.5 m v/ c helps to maintain an output voltage temperature coefficient which is dominated by the temperature coefficients of r2 and r3. in this circuit with 100 ppm/ c tcr resistors, the output voltage exhibits a temperature coefficient of 200 ppm/ c. lower tempco resistors are reco mmended for more accurate performance over temperature. one measure of the performance of a voltage reference is its capability to recover from sudden changes in load current. while sourcing a steady-state load current of 1 ma, this circuit recovers to 0.01% of the programmed output voltage in 1.5 m s for a total change in load current of 1 ma. +2.5v ref p1 5k w 3 2 1 +3v 1/2 op284 8 4 r2 100k w r3 100k w +3v 0.1? r1 17.4k w ad589 resistors = 1%, 100ppm/ c potentiometer = 10 turn, 100ppm/ c figure 50. a +2.5 v reference that operates on a single +3 v supply
rev. 0 C14C op184/op284/op484 a +5 v only, 12-bit dac swings rail-to-rail the op284 is ideal for use with a cmos dac to generate a digitally-controlled voltage with a wide output range. figure 51 shows a dac8043 used in conjunction with the ad589 to gen- erate a voltage output from 0 v to 1.23 v. the dac is actually operating in voltage switching mode where the reference is connected to the current output, i out , and the output voltage is taken from the v ref pin. this topology is inherently noninvert- ing as opposed to the classic current output mode, which is inverting and not usable in single supply applications. v out = (5v) d 4096 r4 100k w 1% 3 2 1 +5v 1/2 op284 8 4 r2 32.4k w 1% r3 232 w 1% r1 17.8k w ad589 gnd clk sr1 ld v ref r fb v dd i out 1.23v 4765 8 2 1 3 dac8043 +5v digital control figure 51. a +5 v only, 12-bit dac swings rail-to-rail in this application the op284 serves two functions. first, it buffers the high output impedance of the dacs v ref pin, which is on the order of 10 k w . the op amp provides a low impedance output to drive any following circuitry. second, the op amp amplifies the output signal to provide a rail-to-rail out- put swing. in this particular case, the gain is set to 4.1 so that the circuit generates a 5 v output when the dac output is at full scale. if other output voltage ranges are needed, such as 0 v v out 4.095 v, the gain can easily be changed by adjusting the values of r2 and r3. a high-side current monitor in the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistors long-term reliability over a wide range of load current conditions. as a result, monitoring and limiting device power dissipation is of prime importance in these designs. the circuit illustrated in figure 52 is an example of a +3 v, single-supply high-side cur- rent monitor that can be incorporated into the design of a volt- age regulator with fold-back current limiting or a high current power supply with crowbar protection. this design uses an op284s rail-to-rail input voltage range to sense the voltage drop across a 0.1 w current shunt. a p-channel mosfet used as the feedback element in the circuit converts the op amps dif- ferential input voltage into a current. this current is then ap- plied to r2 to generate a voltage that is a linear representation of the load current. the transfer equation for the current monitor is given by: monitor output = r 2 r sense r 1 ? ? ? ? i l for the element values shown, the monitor outputs transfer characteristic is 2.5 v/a. 8 1 4 3 +3v 0.1? r sense 0.1 w +3v i l g s d 1/2 ad284 2 m1 si9433 monitor output +3v r2 2.49k w r1 100 w figure 52. a high-side load current monitor capacitive load drive capability the op284 exhibits excellent capacitive load driving capabili- ties. it can drive up to 1 nf as shown in figure 27. however, even though the device is stable, a capacitive load does not come without penalty in bandwidth. the bandwidth is reduced to under 1 mhz for loads greater than 2 nf. a snubber network on the output doesnt increase the bandwidth, but it does sig- nificantly reduce the amount of overshoot for a given capacitive load. a snubber consists of a series r-c network (r s , c s ), as shown in figure 53, connected from the output of the device to ground. this network operates in parallel with the load capaci- tor, c l , to provide the necessary phase lag compensation. the value of the re sistor and capacitor is best determined em pirically. +5v 1/2 op284 r s 50 w c l 1nf c s 100nf v in 100mvp-p 0.1? v out figure 53. snubber network compensates for capacitive load the first step is to determine the value of the resistor r s . a good starting value is 100 w (typically, the optimum value will be less than 100 w ). this value is reduced until the small-signal transient response is optimized. next, c s is determined10 m f is a good starting point. this value is reduced to the smallest value for acceptable performance (typically, 1 m f). for the case of a 10 nf load capacitor on the op284, the optimal snubber network is a 20 w in series with 1 m f. the benefit is immedi- ately apparent as shown in the scope photo in figure 54. the top trace was taken with a 1 nf load, and the bottom trace was taken with the 50 w , 100 nf snubber network in place. the amount of overshoot and ringing is dramatically redu ced. table i below illustrates a few sample snubber networks for large load capacitors.
rev. 0 C15C op184/op284/op484 10 0% 100 90 1nf load only snubber in circuit 2s 50m v 50m v s figure 54. overshoot and ringing is reduced by adding a snubber network in parallel with the 1 nf load table i. snubber networks for large capacitive loads load capacitance snubber network (c l )(r s , c s ) 1 nf 50 w , 100 nf 10 nf 20 w , 1 m f 100 nf 5 w , 10 m f a low dropout regulator with current limiting many circuits require stable regulated voltages relatively close in potential to an unregulated input source. this low dropout type of regulator is readily implemented with a rail-to-rail out- put op amp such as the op284, because the wide output swing allows easy drive to a low saturation voltage pass device. fur- thermore, it is particularly useful when the op amp also enjoys a rail-rail input feature, as this factor allows it to perform high- side current sensing for positive rail current limiting. typical ex- amples are voltages developed from 3 v to 9 v range system sources, or anywhere where low dropout performance is re quired for power efficiency. the 4.5 v case here works from 5 v nomi- nal sources, with worst-case levels down to 4.6 v or less. figure 55 shows such a regulator set up using an op284 plus a low r ds(on) , p-channel mosfet pass device. part of the low dropout performance of this circuit is provided by q1, which has a rating of 0.11 w with a gate drive voltage of only 2.7 v. this relatively low gate drive threshold allows operation of the regulator on supplies as low as 3 v without compromise to over- all performance. the circuit?s main voltage control loop operation is provided by u1b, half of the op284. this voltage control amplifier ampli- fies the 2.5 v reference voltage produced by three terminal u2, a ref192. the regulated output voltage v out is then: v out = v out 2 1 + r 2 r 3 () for the example here, a v out of 4.5 v with v out2 = 2.5 v re- quires a u1b gain of 1.8 times, so r3 and r2 are chosen for a ratio of 1.2:1, or 10.0 k w :8.06 k w (using closest 1% values). note that for the lowest v out dc error, r2 i r3 should be main- tained equal to r1 (as here), and the r2-r3 resistors should be stable, close tolerance metal film types. the table in figure 55 summarizes r1-r3 values for some popular voltages. however, note that in general the output can be anywhere between v out2 to the 12 v maximum rating of q1. while the low voltage saturation characteristic of q1 is a key part of the low dropout, another component is a low current sense comparison threshold with good dc accuracy. here, this is provided by current sense amplifier u1a, which is provided a 20 mv reference from the 1.235 v ad589 reference diode d2 and the r7-r8 divider. when the product of the output current and the r s value matches this voltage threshold, the current control loop is activated, and u1a drives q1?s gate through d1. this causes the overall circuit operation to enter current mode control, with a current limit i limit defined as: i limit = v r ( d 2) r s ? ? ? ? r 7 r 7 + r 8 () r9 27.4k w c4 0.1f c5 0.01f r11 1k w r6 4.99k w r8 301k w +v s r10 1k w r2 8.06k w c3 0.1f r s 0.05 w c6 10f 3 2 1 8 4 r7 4.99k w u1a op284 d2 ad589 d1 1n4148 r5 22.1k w q1 si9433dy r4 2.21k w 6 5 7 c1 0.01f u1b op284 d3 1n4148 2 6 4 3 u2 ref192 c2 1f r1 4.53k w v out 2 2.5v r3 10k w 5.0v 4.5v 3.3v 3.0v 4.99k 4.53k 2.43k 1.69k 10.0k 8.06k 3.24k 2.00k 10.0k 10.0k 10.0k 10.0k v out r1 r2 r3 output table v s > v out + 0.1v optional on/off control input cmos hi (or open) = on lo = off v in common v c v out = 4.5v @ 350ma (see table) v out common figure 55. a low dropout regulator with current limiting
rev. 0 C16C op184/op284/op484 obviously, it is desirable to keep this comparison voltage small, since it becomes a significant portion of the overall dropout voltage. here, the 20 mv reference, is higher than the typical offset of the op284, but still reasonably low as a percentage of v out (< 0.5%). in adapting the limiter for other i limit levels, sense resistor r s should be adjusted along with r7-r8, to main- tain this threshold voltage between 20 mv and 50 mv. performance of the circuit is excellent. for the 4.5 v output version, the measured dc output change for a 225 ma load change was on the order of a few microvolts, while the dropout voltage at this same current level was about 30 mv. the current limit as shown is 400 ma, which allows the circuit to be used at levels up to 300 ma or more. while the q1 device can actually support currents of several amperes, a practical current rating takes into account the so-8 devices 2.5 w, 25 c dissipation. a short circuit current of 400 ma at an input level of 5 v will cause a 2 w dissipation in q1, so other input conditions should be considered carefully in terms of q1s potential overheating. of course, if higher powered devices are used for q1, this circuit can support outputs of tens of amperes as well as the higher v out levels noted above. the circuit shown can be used either as a standard low dropout regulator, or it can also be used with on/off control. by driving pin 3 of u1 with the optional logic control signal v c , the output is switched between on and off. note that when the output is off in this circuit, it is still active (i.e., not an open cir- cuit). this is because the off state simply reduces the voltage input to r1, leaving the u1a/b amplifiers and q1 still a ctive. when on/off control is used, resistor r10 should be used with u1, to speed on-off switching, and to allow the output of the circuit to settle to a nominal zero voltage. components d3 and r11 also aid in speeding up the on-off transition, by providing a dynamic discharge path for c2. off-on transition time is less than 1 ms, while the on-off transition is longer, but under 10 ms. a +3 v, 50 hz/60 hz active notch filter with false ground to process signals in a single-supply system, it is often best to use a false ground biasing scheme. a circuit that uses this approach is illustrated in figure 56. in this circuit, a false-ground circuit biases an act ive notch filter used to reject 50 hz/60 hz power line in terference in portable patient monitoring equip- ment. notch filters are quite commonly used to reject power line frequency interference which often obscures low frequency physiological signals, such as heart rates, blood pressure read- ings, eegs, ekgs, et cetera. this notch filter effectively squelches 60 hz pickup at a filter q of 0.75. substituting 3.16 k w resistors for the 2.67 k w in the twin-t section (r1 through r5) configures the active filter to reject 50 hz interference. 1 3 5 6 7 11 2 +3v r1 2.67k w c1 1? c2 1? r3 2.67k w c3 2? (1? x 2) r4 2.67k w r5 1.33k w (2.67k w ? 2) r2 2.67k w v o r6 10k w v in r8 1k w a2 a1 8 a3 r7 1k w r11 10k w 4 10 9 c5 0.03? r12 150 w r10 20k w c4 1? r9 20k w +3v 1.5v c6 1? a1, a2, a3 = op484 q = 0.75 note: for 50hz applications change r1?4 to 3.1k w and r5 to 1.58k w (3.16k w ? 2). figure 56. a +3 v single supply, 50/60 hz active notch filter with false ground amplifier a3 is the heart of the false-ground bias circuit. it simply buffers the voltage developed at r9 and r10 and is the reference for the active notch filter. since the op484 exhibits a rail-to-rail input common-mode range, r9 and r10 are chosen to split the +3 v supply symmetrically. an in-the-loop compen- sation scheme is used around the op484 that allows the op amp to drive c6, a 1 m f capacitor, without oscillation. c6 maintains a low impedance ac ground over the operating frequency range of the filter. the filter section uses a op484 in a twin-t configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in the twin-t section. mylar is the material of choice for the capacitors, and the relative matching of the capacitors and resistors determines the filters pass band symmetry. using 1% resistors and 5% capacitors produces satisfactory results.
rev. 0 C17C op184/op284/op484 *op284 spice macro-model 9/94 / rev. a * arg/adi * * copyright 1995 by analog devices * * refer to readme.doc file for license statement. use of this model * indicates your acceptance of the terms and provisions in the license * statement. * * node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .subckt op284 1 2 99 50 45 * * input stage * q1 5 2 3 qin 1 q2 6 11 3 qin 1 q3 7 2 4 qip 1 q4 8 11 4 qip 1 dc1 2 11 dc dc2 11 2 dc q5 4 9 99 qip 1 q6 9 9 99 qip 1 q7 3 10 50 qin 1 q8 10 10 50 qin 1 r1 99 5 4e3 r2 99 6 4e3 r3 7 50 4e3 r4 8 50 4e3 iref 9 10 50.5e-6 eos 1 11 poly(2) (22,98) (14,98) -25e-6 1e-2 1 ios 2 1 5e-9 cin 1 2 2e-12 gn1 98 1 (17,98) 1e-3 gn2 98 2 (23,98) 1e-3 * * voltage noise source with flicker noise * vn1 13 98 dc 2 vn2 98 15 dc 2 dn1 13 14 den dn2 14 15 den * * current noise source with flicker noise * vn3 16 98 dc 2 vn4 98 18 dc 2 dn3 16 17 din dn4 17 18 din * * 2nd current noise source with flicker noise * vn5 19 98 dc 2 vn6 98 24 dc 2 dn5 19 23 din dn6 23 24 din * * gain stage * eref 98 0 poly(2) (99,0) (50,0) 0 0.5 0.5 g1 98 20 poly(2) (6,5) (8,7) 0 0.5e-3 0.5e-3 r9 20 98 1e3 * * common mode stage with zero at 100hz * ecm 98 21 poly(2) (1,98) (2,98) 0 0.5 0.5 r10 21 22 1 r11 22 98 100e-6 c4 21 22 1.592e-3 * * negative zero at 20mhz * e1 27 98 (20,98) 1e6 r17 27 28 1 r18 28 98 1e-6 c8 25 26 7.958e-9 enz 25 98 (27,28) 1 vnz 26 98 dc 0 fnz 27 28 vnz -1 * * pole at 40mhz * g4 98 29 (28,98) 1 r19 29 98 1 c9 29 98 3.979e-9 * * pole at 40mhz * g5 98 30 (29,98) 1 r20 30 98 1 c10 30 98 3.979e-9 * * outut stage * isy 99 50 0.276e-3 gin 50 31 poly(1) (30,98) .862574e-6 505.879e-6 rin 31 50 2.75e6 vb 99 32 0.7 q11 32 31 33 qon 1 r21 33 34 4.5e3 i1 34 50 50e-6 r22 99 35 6e3 q12 36 36 35 qop 1 i2 36 50 50e-6 r23 99 37 2.6e3 r24 34 38 5e3 q13 39 36 37 qop 1 q14 39 38 40 qon 1.5 r25 40 50 40 q15 39 39 41 qon 1 r26 41 42 1e3 r27 99 43 220 q16 44 44 43 qop 1.5 q17 44 39 42 qon 1 r28 42 50 2e3 vscp 99 97 dc 0
rev. 0 C18C op184/op284/op484 fscp 46 99 vscp 1 rscp 46 99 40 q20 44 46 99 qop 1 q18 45 44 97 qop 4.5 q19 45 34 51 qon 4.5 vscn 51 50 dc 0 fscn 50 47 vscn 1 rscn 47 50 40 q21 34 47 50 qon 1 cc2 31 45 20e-12 cf1 31 34 15e-12 cf2 31 42 15e-12 co1 34 45 15e-12 co2 42 45 5e-12 d3 45 99 dx d4 50 45 dx .model dc d(is=130e-21) .model dx d() .model den d(rs=100 kf=12e-15 af=1) .model din d(rs=5.358 kf=56e-15 af=1) .model qin npn(bf=200 va=200 is=0.5e-16) .model qip pnp(bf=100 va=60 is=0.5e-16) .model qon npn(bf=200 va=200 is=0.5e-16 rc=50) .model qop pnp(bf=200 va=200 is=0.5e-16 rc=160) .ends
rev. 0 C19C op184/op284/op484 14-lead epoxy dip (p suffix) 14 17 8 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 14-lead narrow-body so (s suffix) 14 8 7 1 0.3444 (8.75) 0.3367 (8.55) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 8-lead epoxy dip (p suffix) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead so (s suffix) 85 4 1 0.1968 (5.00) 0.1890 (4.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 outline dimensions dimensions shown in inches and (mm).
printed in u.s.a. c2167C18C9/96 C20C

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